1. Field of the Invention
The present invention relates to Flash memory devices. More particularly, the present invention relates to an address-transition detector for a Flash memory device.
2. The Prior Art
The consistency of the pulse width in flash memory devices that perform read operations at the speed of 20 ns, or equivalently in the 50 MHz range is extremely important. Existing designs are not suitable for read speed at this frequency, because the timing variation becomes rather significant in this new environment.
U.S. Pat. No. 4,633,102 discloses a scheme in which the output pulse width varies with the rise time and fall time of the input signal. It is believed that this design is unable generate a constant timing pulse.
U.S. Pat. No. 4,742,247 discloses an address-transition-detector that has good temperature compensation.
U.S. Pat. No. 4,922,461 discloses a pulse generator driving a clock generator.
U.S. Pat. No. 4,982,117 discloses an address-transition-detector that ends its pulse width whenever a transition occurs at the output.
U.S. Pat. No. 5,057,712 discloses an address-transition-detector having a pulse width that suffers from VCC, temperature and process variations.
Since flash memory products perform read operations at less than 50 MHz, there is no alternative design or method used in the industry. Thus, a new design that serves this need is desired to meet such a design requirement.